Data Connect DSP19.2 Betriebsanweisung

Full-Speed USB (12 Mbps) PeripheralController with Integrated HubCY7C66013C CY7C66113CCypress Semiconductor Corporation • 198 Champion Court • San Jo

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 10 of 613.0 Pin Configurations123456791112131415161817XTALIN10819203938374140434245444746494

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 11 of 61Figure 3-1. CY7C66113C 56-pin QFN Pin Assignment 282726252423222120191817161543444546

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 12 of 61Figure 3-2. CY7C66113C DIE Cypress LogoPin 1Pin 60Pin 15Pin 30 Pin 45(0,0)(3398, 4194

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 13 of 61Table 3-1. Pad Coordinates in microns (0,0) to bond pad centersPad # Pin Name X Y Pa

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 14 of 614.0 Product Summary Tables4.1 Pin Assignments 4.2 I/O Register SummaryI/O registers

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 15 of 61GPIO Configuration 0x08 R/W GPIO Port Configurations 23HAPI and I2C Configuration 0x0

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 16 of 614.3 Instruction Set SummaryRefer to the CYASM Assembler User’s Guide for more details

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 17 of 615.0 Programming Model5.1 14-bit Program Counter (PC)The 14-bit Program Counter (PC)

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 18 of 615.1.1 Program Memory Organization after reset Address 14-bit PC 0x0000Program execut

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 19 of 615.2 8-bit Accumulator (A)The accumulator is the general-purpose register for the micr

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 2 of 61TABLE OF CONTENTS1.0 FEATURES ...

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 20 of 61For USB applications, the firmware should set the DSP to an appropriate location to a

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 21 of 612 cm). A 6-MHz fundamental frequency parallel resonant crystal can be connected to th

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 22 of 61The USB transmitter is disabled by a WDR because the USB Device Address Registers are

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 23 of 61There are up to 31 GPIO pins (P0[7:0], P1[7:0], P2[7:0], and P3[6:0]) for the hardwar

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 24 of 61As shown in Table 9-1 below, a positive polarity on an input pin represents a rising

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 25 of 61Port 1 Interrupt Enable ADDRESS 0x05Port 2 Interrupt Enable ADDRESS 0x06Port 3 Interr

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 26 of 61are set to ‘0’ when the device is suspended, that DAC input will float. The floating

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 27 of 61Bit [7..0]: Polarity bit x (x= 0..7)1= Selects positive polarity (rising edge) that c

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 28 of 61Bits [7,1:0] of the HAPI/I2C Configuration Register control the pin out configuration

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 29 of 61The I2C Status and Control register bits are defined in Table 13-1, with a more detai

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 3 of 6116.0 INTERRUPTS ...

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 30 of 61Bit 1: Receive StopThis bit is set when the slave is in receive mode and detects a st

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 31 of 6115.0 Processor Status and Control RegisterProcessor Status and Control ADDRESS 0xFFB

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 32 of 61Global Interrupt Enable Register ADDRESS 0X20Bit 0: USB Bus RST Interrupt Enable1 = E

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 33 of 61When servicing an interrupt, the hardware does the following:1. Disables all interrup

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 34 of 61 16.2 Interrupt LatencyInterrupt latency can be calculated from the following equatio

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 35 of 61the transaction (e.g., on the host’s ACK during an IN, or on the device ACK during on

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 36 of 6116.9 I2C InterruptThe I2C interrupt occurs after various events on the I2C-compatible

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 37 of 61which (if any) of the downstream ports need to be enumerated. The following is a brie

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 38 of 61Hub Ports Connect Status ADDRESS 0x48Bit [0..3]: Port x Connect Status (where x = 1..

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 39 of 6118.3 Hub Downstream Ports Status and ControlData transfer on hub downstream ports is

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 4 of 61LIST OF FIGURESFigure 3-1. CY7C66113C 56-pin QFN Pin Assignment ...

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 40 of 61Hub Ports Data ADDRESS 0x50Bit [0..3]: Port x Diff Data (where x = 1..4)Set to 1 if

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 41 of 611. Hardware detects the Resume, drives a K to the port, and generates the hub interru

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 42 of 61Bit 3: Bus Activity This is a “sticky” bit that indicates if any non-idle USB event

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 43 of 61When the SIE writes data to a FIFO, the internal data bus is driven by the SIE; not t

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 44 of 6119.4 USB Non-Control Endpoint Mode RegistersThe format of the non-control endpoint mo

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 45 of 61SETUP:The SETUP bit of the endpoint 0 mode register is forced HIGH at this time. This

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 46 of 61ACK1. IN TokenHOSTDEVICESYNCINADDRCRC5ENDPSYNCDATA1/0CRC16SYNCDataToken Packet Data P

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 47 of 6120.0 USB Mode TablesModeThis lists the mnemonic given to the different modes that ca

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 48 of 61CommentsSome Mode Bits are automatically changed by the SIE in response to certain US

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 49 of 61 Table 20-3. Details of Modes for Differing Traffic Conditions (see Table 20-2 for t

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 5 of 61LIST OF TABLESTable 3-1. Pad Coordinates in microns (0,0) to bond pad centers ...

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 50 of 611 1 1 1 In x UC x UC UC UC UC 1 UC 1 1 110ACK (back)yesNak In/premature status Out1 1

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 51 of 61 1 1 0 0 In x UC x UC UC UC UC 1 UC UC No ChangeNAK yesIsochronous endpoint (In)0 1 1

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 52 of 61INTERRUPT0x20 Global InterruptEnableReserved I2CInterrupt EnableGPIOInterrupt EnableD

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 53 of 6122.0 Sample SchematicXTALOXTALID0–D0+D1+D1–D2–D2+D3–D3+D4–D4+VccVrefVppGNDGNDINGNDOU

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 54 of 6123.0 Absolute Maximum RatingsStorage Temperature ...

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 55 of 61VOHOutput High Voltage IOH = 1.9 mA (all ports 0,1,2,3) 2.4 VDAC InterfaceRupDAC Pul

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 56 of 61 CLOCKtCYCtCLtCHFigure 25-1. Clock Timing90%10%90%10%D−D+trtrFigure 25-2. USB Data

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 57 of 6126.0 Ordering InformationOrdering Code PROM Size Package Type Operating RangeCY7C660

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 58 of 6127.0 Package Diagrams 48-pin Shrunk Small Outline Package O4851-85061-*C56-pin Shrun

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 59 of 6128.0 Quad Flat Package No Leads (QFN) Package Design NotesElectrical contact of the

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 6 of 611.0 Features• Full-speed USB peripheral microcontroller with an integrated USB hub—We

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 60 of 61© Cypress Semiconductor Corporation, 2006. The information contained herein is subjec

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 61 of 61Document History PageDocument Title: CY7C66013C, CY7C66113C Full-Speed USB (12 Mbps)

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 7 of 612.0 Functional OverviewThe CY7C66013C and CY7C66113C are compound devices with a full

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 8 of 612.8 InterruptsThe microcontroller supports eleven maskable interrupts in the vectored

CY7C66013C CY7C66113CDocument #: 38-08024 Rev. *B Page 9 of 61 Logic Block DiagramInterruptControllerPROM12-bitTimerResetWatchdogTimerRepeaterPower-